The present invention relates generally to field programmable circuits as related to three-dimensional integration and, more particularly, to a programmable via structure suitable for use in three-dimensional integration technology.
Traditionally, application specific integrated circuit (ASIC) devices have been used in the integrated circuit (IC) industry to reduce cost, enhance performance or meet space constraints. The generic class of ASIC devices falls under a variety of sub classes such as custom ASICs, standard cell ASICs, Gate Array, and Field Programmable Gate Array (FPGA), wherein the degree of user allowed customization varies.
In recent years, there has been a move away from custom, semi-custom and Gate Array ICs toward field programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user “in the field” prior to use. Off the shelf FPGA products greatly simplify the design cycle and are fully customized by the user. These products offer user-friendly software to fit custom logic into the device through programmability, and the capability to tweak and optimize designs to improve silicon performance. While such programmability is expensive in terms of silicon real estate, it reduces design cycle time, time to solution (TTS) and upfront non-recurring engineering (NRE) costs to the designer.
Reconfigurable circuits, such as FPGAs, are also anticipated to play a significant role in the new Three Dimensional Integration (3DI) technology currently under development. In planar circuit technologies (i.e., the individual circuit elements are formed on a single, planar substrate), an FPGA 100 (as shown in FIG. 1) is characterized by a set of simple, configurable logic blocks 102 arranged in an array with interspersed switches 104 that can rearrange the interconnections between the logic blocks 102.
In contrast, 3DI structures (such as shown in FIG. 2) consist of multiple semiconductor layers (DL1, DL2, etc.) that are interconnected in a vertical direction. In a multilayer logic network, this three-dimensionality may be exploited to increase density without reducing feature size, and reduce the line of flight interconnect path between logic elements. Optimal communication efficiency can thus be achieved in this context by introducing reconfigurable interconnects. Reconfigurable interconnects also offer the possibility for multi-use chips, thereby enabling compatibility with different communication protocols. Moreover, technologically disparate multilayer structures can form unique, single-chip combinations such as (logic+memory), (logic+optical communications) and (logic+sensors), for example. In these types of multicomponent/multilayer systems, reconfigurable connections are therefore needed to provide the controllable logic functionality, memory element repair and data encryption, etc.
Existing field-programmable logic and memory repair technology utilizes several methods to physically make/break the connections between logic blocks; unfortunately, none of these existing methods provides a fully adequate solution to the requirements of a 3DI application. For instance, a laser-fusible link is an early approach, but has now replaced by electrical techniques entirely internal to the chip. Electromigration fuses, such as those in IBM's eFUSE technology for rerouting chip logic, are also currently in use. However, an electromigration fuse takes up a large circuit area and requires a high current to blow the fuse. Moreover, the process is “one-shot,” i.e., once the fuse is blown, it cannot thereafter be returned to a conducting state. Further, the distribution of eFuse characteristics is relatively broad, requiring that the state of each fuse be sensed by a discriminating circuit with the digital result stored in a latch.
Another existing approach for FPGA is the use of flash bits to control a pass transistor for each interconnection. A flash bit takes up space in the logic level, is formed by a process that is incompatible with standard CMOS processing, and requires a special high voltage to charge the gate oxide. As compared to a laser-blown fuse or an eFuse, the flash approach is considered limited multi-shot technique (e.g., about 20,000 reversals).
An anti-fuse approach used for some DRAM repair typically involves a very thin dielectric material such as silicon dioxide, or the sandwich combination silicon oxide-nitride-oxide (ONO), between two conductors. The anti-fuse is programmed by applying a relatively high voltage through the conducting terminals, thus causing dielectric breakdown in the dielectric. As a result, the resistance of the anti-fuse permanently changes from high to low. Accordingly, this represents another example of a one-shot technique, one that requires a high voltage.
The controllable link technologies described above do not have optimal properties for programmable logic applications in 3DI (or even for planar applications for that matter). In particular, a dependency on the use of high voltages (whether for gate charging in flash bit applications or for dielectric antifuses) is undesirable. In the case of flash bits, their presence in the logic level real estate may cause process incompatibilities, as described above. Electromigration fuses driven by relatively high current are large-area, require undesirably high power, and require an additional discriminator and latch circuitry. Furthermore, devices incorporating static RAM latches are subject to soft error arising from alpha particles or cosmic rays, which in a 3DI application may also have the effect of randomly altering the logic configuration. With the exception of flash bit technology (which has limited multi-shot capability), conventional fuse-based approaches are one-shot.
Accordingly, it would therefore be desirable to be able to configure a programmable link for a 3DI application that does not require high current or voltage to program, that is compatible with standard CMOS processing at the device level, that avoids the need for an SRAM latch to minimize space and avoid soft errors, and that is reprogrammable for a significant number of multiple instances (i.e., not single-shot).